1. Field of the Invention
The present invention relates to an integrated semiconductor device including high-voltage interconnections passing through low-voltage regions.
2. Description of the Related Art
As is known, passage of high-voltage interconnections on integrated circuits of semiconductor material, such as silicon, at voltages of over 100 V requires the adoption of sophisticated solutions at layout and process levels to overcome the effects of the charge induced in the semiconductor material and of charge movements in the dielectrics. In fact, in these situations, malfunctioning may occur in the integrated circuits.
The simplest solutions currently implemented to overcome the above-mentioned effects comprise providing field plates, i.e., electrostatic shields of semiconductor material, typically doped polycrystalline silicon or metal, extending between the interconnection lines and the areas to be protected. These field plates modify the electric field existing in critical areas, such as the insulations for positive-potential interconnections and Nxe2x88x92 doped areas for negative-potential interconnections.
In addition, the thickness of the dielectric layer on which the interconnections extend increases as the voltages carried by the interconnections increase. Beyond a certain voltage value, however, the thickness becomes considerable and not always compatible with present processes and dimensional requirements. Consequently, whenever possible, the interconnections are made in xe2x80x9cbridgexe2x80x9d fashion, using bonding wires.
Particular problems are encountered in case of high voltages supplied to parts of devices formed on various wafers some of which are low-voltage ones. In this case, in fact, the various wafers house different parts of the device which are to be electrically and mechanically connected through bonding structures.
In particular, in these devices, the various parts are connected by interconnections of metal and strongly doped silicon which must be able to withstand high voltages and confine them so as to prevent the high electric fields associated thereto from damaging or hindering proper operation of the low-voltage parts.
An embodiment of the present invention overcomes the limitations of the prior art by providing an interconnection system in a device formed in various wafers and including high-voltage parts and low-voltage parts.
According to an embodiment of the present invention, an integrated semiconductor device is provided, including a first chip of semiconductor material having first high-voltage regions at a first, high-value, voltage,
a second chip of semiconductor material having second high-voltage regions at said first, high-value, voltage,
a third chip of semiconductor material extending between said first and second chip and having at least one low-voltage region at a second, low-value, voltage,
a through connection region formed in said third chip and connected to at least one of said first and second high-voltage regions, and through insulating regions surrounding and insulating said through connection region.
A method of operation is also provided, according to an embodiment of the invention.